Presentations
Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Shuang Liang
Dual Mode Logic Address Decoder
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Netanel Shavit
Fast Packet Classification Using RISC-V and HyperSplit Acceleration on FPGA
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Arsinoe Pnevmatikou
Simulation and Formal: the Best of Both Domains for Instruction Set Verification of RISC-V Based Processors
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Ckristian Duran
Author(s): Ckristian Duran, Hanssel Morales, Camilo Rojas, Annachiara Ruospo, Ernesto Sanchez, Elkim Roa
Unified Characterization Platform for Emerging NVM Technology: Neural Network Application Benchmarking Using Off-the-Shelf NVM Chips
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Supriya Chakraborty
Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Benjamin Carrion Schafer
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Dongwon Park
MLIP Cores: Designing Hardware Generators with Programmable Microarchitectural Mechanisms
Presented Date:Jul 07, 12:14pm UTCPresenter(s): Alexander Antonov
Chairs
Chair(s)
![Baris Taskin Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/1200002.jpg?h=45b0c289&itok=enW0KByQ)
Display Name
Baris Taskin
- Affiliation
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AffiliationDrexel University
- Country
![Adam Teman Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/1770002.jpg?h=fbf7a813&itok=Ej8ziHH6)
Display Name
Adam Teman
- Affiliation
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AffiliationBar-Ilan University
- Country