Performance demands in communications technology is driving research towards advanced network processors, which are able to handle huge rates of incoming packets via application-specific circuits, however, without sacrificing all of the conventional CPU flexibility. At the same time, the advent of RISC-V is disrupting the industry & academia by opening computer architecture to a broader research community. Combining the above, the current paper considers placing dedicated VHDL accelerators next to a RISC-V processor to accommodate network functions via customized HW/SW co-processing. We extend the ISA with a new instruction to perform search tree operations that accelerate Packet Classification tasks in routers. For rapid prototyping and design exploration, we implement the binary search of HyperSplit algorithm on an Xilinx Ultrascale xcku060 FPGA. Our design achieves 125x faster classification than RISC-V alone and sustains up to 13.5M packets/sec throughput.