With the scaling of VLSI technologies, the design technology co-optimization (DTCO) requires prompt development of standard cell libraries to explore scaling effects of various cell architectures. However, standard cell layout design demands holistic efforts for processing transistor placement and in-cell routing due to the limited routing tracks and complicated design rules. Thus, an automatic design framework of standard cell layout became essential in the advanced scaling. Conventional heuristic/divide-and-conquer approaches lack the optimality of solutions because of the limited solution space. In this paper, we propose a novel standard cell scaling framework that simultaneously finds an optimal solution in placement and routing with the pin-accessibility. To ensure the minimum number of pin-access points, we devise strict Boolean counter-based design constraints. We validate our framework using scaling parameters and cell architectures across sub-7nm technology nodes.