Address decoders are integral components of random access memories. The timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. We present a novel Dual Mode Logic (DML) based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product at nominal VDD=0.8V compared to static CMOS address decoder. DML based address decoder exhibits low susceptibility to process variation and supports robust operation in a wide supply voltage range. This is the first time DML is evaluated in 16nm FinFet process.