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Presentations
A Templated VHDL Architecture for Terabit/s P4-Programmable FPGA-Based Packet Parsing
Presented Date:Jun 30, 06:58pm UTCID: 1575
Presenter(s): Parisa Mashreghi-Moghadam
MinAC: Minimal-Area Approximate Compressor Design Based on Exact Synthesis for Approximate Multipliers
Presented Date:Jun 30, 06:58pm UTCID: 1639
Presenter(s): Xuan Wang
Artificial Neural Network Based Post-CTS QoR Report Prediction
Presented Date:Jun 30, 06:58pm UTCID: 1723
Presenter(s): Arpit Jain
A 0.45 pJ/Bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators
Presented Date:Jun 30, 06:58pm UTCID: 1744
Presenter(s): Baris Taskin
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer
Presented Date:Jun 30, 06:58pm UTCID: 1745
Presenter(s): Baris Taskin
Chairs
Chair(s)
Display Name
Ricardo Reis
- Affiliation
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AffiliationUniversidade Federal do Rio Grande do Sul
- Country