Presentations
An Efficient Low Cost FPGA MIMO Channel Model
Presented Date:Jul 05, 02:10pm UTCID: 6014
Presenter(s): Oluyomi Simpson
Accelerated Piece-Wise-Linear Implementation of Floating-Point Power Function
Presented Date:Jul 05, 02:10pm UTCID: 6197
Presenter(s): NANDAGOPAL RAJASEKARAN
Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI
Presented Date:Jul 05, 02:10pm UTCID: 6252
Presenter(s): Minoru Watanabe
Efficient LoRa-Like Transmitter Stacks for SDR Applications
Presented Date:Jul 05, 02:10pm UTCID: 6321
Presenter(s): Léa Volpin
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators
Presented Date:Jul 05, 02:10pm UTCID: 6174
Presenter(s): GABRIELE MONTANARO
A Trusted Communication Unit for Secure Tiled Hardware Architectures
Presented Date:Jul 05, 02:10pm UTCID: 6043
Presenter(s): Sebastian Haas
Chairs
Chair(s)
Display Name
Maurizio Valle
- Affiliation
-
AffiliationUniversity of Genova
- Country
Display Name
Edoardo Ragusa
- Affiliation
-
AffiliationUniversity of Genoa
- Country