Modern hardware and software in smart systems and devices need to provide high performance and energy efficiency and, at the same time, properly address security and privacy goals. M³ proposed a system architecture that integrates cores and accelerators within a tiled hardware architecture using a security-by-design approach. Each tile includes a hardware component called trusted communication unit (TCU), which isolates all tiles from each other so that no communication is possible by default. In this paper, we designed, developed, and synthesized the hardware components of the M³ system architecture comprising a network-on-chip, RISC-V cores, and TCUs. Latency measurements show that the timing overhead introduced by the data transfer and security features of the TCU is not significant compared to other latencies like cache accesses or software routines. Synthesis results reveal that the area overhead of the trusted system components is only 11% when the system is scaled to a high number of processing tiles.