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Presentations
A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise
Presented Date:Jul 04, 06:09pm UTCID: 1395
Presenter(s): Min Li
A Ring-Oscillator Sub-Sampling PLL with Hybrid Loop Using Generator-Based Design Flow
Presented Date:Jul 04, 06:09pm UTCID: 1287
Presenter(s): Zhongkai Wang
Author(s): Zhongkai Wang, Minsoo Choi, John Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, Sijun Du, Elad Alon
A Batch Bayesian Optimization Approach for Analog Circuit Synthesis Based on Multi-Points Selection Criterion
Presented Date:Jul 04, 06:09pm UTCID: 1385
Presenter(s): Xu Fu
Variation-Aware Analog Circuit Sizing in Carbon Nanotube
Presented Date:Jul 04, 06:09pm UTCID: 2023
Presenter(s): Zahra Heshmatpour
Fogging-Effect-Aware Mixed-Signal IC Placement with Reinforcement Learning
Presented Date:Jul 04, 06:09pm UTCID: 2039
Presenter(s): Mohammad Hajijafari
Chairs
Chair(s)
Display Name
Sohmyung Ha
- Affiliation
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AffiliationNew York University Abu Dhabi
- Country
Display Name
lababidi raafat
- Affiliation
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AffiliationENSTA Bretagne
- Country