Although being deemed as one of the promising candidates to substitute CMOS transistors in the sub-10 nm regime, fabrication of Carbon Nanotube Field-Effect Transistors (CNFET) is still experiencing significant process variations. In this paper, we consider carbon nanotube parameter process variations in CNFET analog circuit sizing design. To the best of our knowledge, this is the first work that systematically studies a robust sizing methodology for analog CNFET circuits. We propose a multi-objective deterministic sizing flow to reach the best performance of analog CNFET circuits even under device parameter process variation. We use a design centering approach to obtain the optimal value of design parameters to ensure a robust circuit. By using SPICE simulation for circuit performance verification, we have developed a generic multi-objective deterministic sizing optimization methodology by combining generalized boundary curve and normal boundary intersection schemes. The experimental results demonstrate that our proposed method can better estimate the Pareto front compared to the other state-of-the-art multi-objective alternatives.