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Presentations
Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator
Presented Date:Jul 04, 06:04pm UTCPresenter(s): Weikang Qian
Efficient Fast-SCAN Flip Decoder for Polar Codes
Presented Date:Jul 04, 06:04pm UTCPresenter(s): Leyu Zhang
A Semi-Folded Decoding Architecture for Flexible Codeword Length Configuration of Polar Codes
Presented Date:Jul 04, 06:04pm UTCPresenter(s): Limin Jiang
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers
Presented Date:Jul 04, 06:04pm UTCPresenter(s): Danyang Zhu
Design Considerations for a Sub-25µW PLL with Multi-Phase Output and 1-450MHz Tuning Range
Presented Date:Jul 04, 06:04pm UTCPresenter(s): Baibhab Chatterjee
Chairs
Chair(s)
Display Name
Chuan Zhang
- Affiliation
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AffiliationSoutheast University, China
- Country
Display Name
Zhongfeng Wang
- Affiliation
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AffiliationNanjing University, China
- Country