Approximate computing improves the energy effificiency of circuits by introducing some errors. In this paper, we advocate a method that integrates approximate logic synthesis (ALS) into the design loop of low-power NN accelerators. ALS automatically synthesizes a good approximate circuit and can take input distribution into consideration. So the NN computation pattern can be exploited to design an approximate multiplier that fits better with the NN. The results show that this method can generate an extremely small approximate multiplier with area only 4.2% of the accurate version, while it can still enable a high accuracy of 97.9% on MNIST dataset.