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Presentations
A Digital Bit-Reconfigurable Versatile Compute-in-Memory Macro for Machine Learning Acceleration
Presented Date:Jul 03, 01:43am UTCID: 1788
A Ternary Neural Network Computing-In-Memory Processor with 16T1C Bitcell Architecture
Presented Date:Jul 03, 01:43am UTCID: 1223
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator
Presented Date:Jul 03, 01:43am UTCID: 1262
REGAL : Reprogrammable Engines for Genome Analysis on LPDDR4x-Based Stacked DRAM
Presented Date:Jul 03, 01:43am UTCID: 1694
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing
Presented Date:Jul 03, 01:43am UTCID: 1160
Author(s): Qibang Zang, Wang Ling Goh, Lu Lu, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do
Chairs
Chair(s)
Display Name
Boris Vaisband
- Affiliation
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AffiliationMcGill University
- Country
Display Name
Tony Tae-Hyoung Kim
- Affiliation
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AffiliationNanyang Technological University
- Country