Compute in memory (CiM) is a promising solution for solving the bottleneck frequent data interface between memory and processor in Von-Neumann architecture. In this work, a hybrid current/charge domain 7T-SRAM based CiM architecture is proposed to reduce the RBL variation and better linearity during computation without significantly impact the operating frequency and area overhead. Additionally, a column referenced 1-5b reconfigurable SAR ADC is proposed to support configurable multi-bit output activation. The largest RBL variation (σ) is 2.08 mV, resulting in a MNIST classification accuracy of 97.5% which is a 0.1% degradation compared to the baseline without variation and Google Speech Command classification accuracy of 80.5% which is a 0.5% degradation compared to the baseline without variation. The whole architecture offers an energy efficiency of 282-to-607 TOPS/W for 1-5b MAC operation, respectively, which is competitive when compared to other state-of-art CiM architectures.