Technology scaling and charge-sharing make nano-scale CMOS latches become severely vulnerable to multiple-node upset (MNU). This paper proposes a triple-path dual-interlocked-storage-cell (TPDICE) and soft-error interceptive module (SIM) based 4-Node-Upset (4NU) completely hardened latch, namely 4NUHL latch, that can completely tolerate soft errors, such as 4NUs. The latch mainly consists of 2 TPDICE and a 3-level SIM which comprises six 2-input C-elements. Owing to the single-node-upset self-recoverability and multiple storage nodes of TPDICEs and the soft-error interception capability of the SIM, the latch can provide complete 4NU tolerance. Simulation results demonstrate that the proposed 4NUHL latch is completely 4NU hardened. Furthermore, we use a high-speed path, clock-gating, and a few transistors to reduce overhead of the proposed latch. We compared the proposed latch with the state-of-the-art hardened latches in terms of reliability and overhead to demonstrate advancement of the proposed latch.