CMOS circuits operating at cryogenic temperature are gaining interest as one of the most promising approaches to efficiently scale up quantum processors in near- and medium future. Quantum processors has faced several challenges such as power consumption and changes in transistor behaviors due to the shift of systems toward dilution fridge. Hence, for optimization of conventional memory systems at cryogenic temperature, analyzing memory cells(SRAM) at cryogenic temperature is necessary. This paper shows that despite of increase of threshold voltage in cryogenic temperature, it is still possible to operate the SRAM at low-voltage for power saving in quantum computing applications.