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Presentations
Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks
Presented Date:Jul 08, 01:35pm UTCPresenter(s): Vinay Joshi
A 0.82 µW CIS-Based Action Recognition SoC with Self-Adjustable Frame Resolution for Always-on IoT Devices
Presented Date:Jul 08, 01:35pm UTCPresenter(s): Junha Ryu
Saturation RRAM Leveraging Bit-Level Sparsity Resulting from Term Quantization
Presented Date:Jul 08, 01:35pm UTCPresenter(s): Bradley McDanel
Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI
Presented Date:Jul 08, 01:35pm UTCPresenter(s): Kohji Hosokawa
Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors
Presented Date:Jul 08, 01:35pm UTCPresenter(s): Siddhartha Raman Sundara Raman
Chairs
Chair(s)
![Vishal Saxena Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/2539001.jpg?h=589afc61&itok=m6Hr6VkT)
Display Name
Vishal Saxena
- Affiliation
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AffiliationUniversity of Delaware
- Country
![Aatmesh Shrivastava Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/AS.jpg?h=201e2d68&itok=qLFykoXl)
Display Name
Aatmesh Shrivastava
- Affiliation
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AffiliationNortheastern University, Boston, MA
- Country