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Presentations
A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture with Delayed Feedback
Presented Date:Jul 07, 10:54am UTCPresenter(s): Ju-Hye Han
A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs
Presented Date:Jul 07, 10:54am UTCPresenter(s): Dong-Jick Min
Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications
Presented Date:Jul 07, 10:54am UTCPresenter(s): Jingying Zhang
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC
Presented Date:Jul 07, 10:54am UTCPresenter(s): Yuekang Guo
A 1st-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration
Presented Date:Jul 07, 10:54am UTCPresenter(s): Hanrui Zhang
Chairs
Chair(s)
Display Name
Tawfiq Musah
- Affiliation
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AffiliationOhio State University
- Country
Display Name
Jose M. de la Rosa
- Affiliation
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AffiliationInstituto de Microelectronica de Sevilla
- Country