This paper presents a second-order discretetime (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer's input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the internal FF path and reduces the number of input signals of the adder. A 4-bit asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporated with a passive adder is used to reduce power consumption and area. To allow the conversion delay of the SAR ADC, a delayed feedback is adopted. The prototype ADC is fabricated in a 0.11μm CMOS process using four metal layers with an active die area of 0.165mm2. It achieves a dynamic range (DR) of 96.3 dB and a peak signal-tonoise and distortion ratio (SNDR) of 93.9 dB in a 2 kHz signal bandwidth while consuming 62.43μW from a 1.8V/1.65V power supply, corresponding to a Schreier figure-of-merit (FOM) of 171 dB.