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Presentations
MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators
Presented Date:Jul 04, 04:55pm UTCID: 14
Presenter(s): Vasileios Leon
Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA
Presented Date:Jul 04, 04:55pm UTCID: 26
Presenter(s): Gracieth Batista
PPA Based CNN Architecture Explorer
Presented Date:Jul 04, 04:55pm UTCID: 36
Presenter(s): Dinesh Bhatia
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design
Presented Date:Jul 04, 04:55pm UTCID: 46
Presenter(s): Guilherme Barbosa Manske
Chairs
Chair(s)
Display Name
Dinesh Bhatia
- Affiliation
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AffiliationThe University of Texas at Dallas
- Country
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CountryUnited States