LASCAS 2022
|
Technical Lecture and Demo
ID 46

Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design
Details
Presenter(s)
Guilherme Barbosa Manske Headshot
Guilherme Barbosa Manske
Affiliation
Universidade Federal de Pelotas - UFPel
Country
Brazil
View profile
Author(s)
Henrique Kessler
Affiliation
Universidade Federal de Pelotas
View profile
Murilo Bohlke
Affiliation
Federal University of Pelotas
View profile
Leomar Rosa Jr.
Affiliation
Universidade Federal de Pelotas
View profile
Marcelo Porto
Affiliation
Universidade Federal de Pelotas
View profile
Vinícius V. Camargo
Affiliation
Universidade Federal de Pelotas
View profile
Slides
  • Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design (application/pdf)
    Download