Time-correlated single-photon counting (TCSPC) 3D imaging requires the digitization of photon arrival times across an array of single-photon avalanche diodes (SPADs). The most critical performance metrics of time-to-digital converters (TDC) in TCSPC applications are their conversion rate (CR), area, and power consumption. This paper presents a multi-channel RO-based TDC architecture whose power consumption scales with its configurable resolution for power-sensitive applications. Further power savings are achieved by sharing one RO among multiple TDC channels. We have demonstrated that sharing one RO among five channels reduces the power consumption by more than 75% relative to non-shared architectures. Here, a 5-channel 12-bit TDC is fabricated in 65 nm CMOS with an area of 1920 um2 per channel. It demonstrates CR up to 125 MHz and offers a resolution configurable over the range of 24–133 ps. At a CR of 125 MHz, the TDC power consumption per channel is 0.1 mW and 1 mW per channel at 133 ps and 24 ps resolution, respectively.