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Presentations
SaGNN: A Sample-Based Gnn Training and Inference Hardware Accelerator
Presented Date:Jul 08, 03:54am UTCID: 1298
An Area-Efficient Memory-Based Architecture for P4-Programmable Streaming Parsers in FPGAs
Presented Date:Jul 08, 03:54am UTCID: 1447
SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs
Presented Date:Jul 08, 03:54am UTCID: 1920
Radiation-Hardened Triple-Modular Redundant Field Programmable Gate Array with a Two-Phase Clock
Presented Date:Jul 08, 03:54am UTCID: 2223
Author(s): Minoru Watanabe
A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices
Presented Date:Jul 08, 03:54am UTCID: 1502
Chairs
Chair(s)
Display Name
Chung-An Shen
- Affiliation
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AffiliationNational Taiwan University of Science and Technology
- Country
Display Name
Darshika G. Perera
- Affiliation
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AffiliationUniversity of Colorado at Colorado Springs - USA
- Country