Network flexibility and reconfigurability are crucial for software-defined networking and function virtualization. Packet parsing, the first packet processing stage, requires high performance and reconfigurability to allow implementing low-latency and flexible networks. This paper proposes an overlay architecture for an FPGA-based P4-programmable streaming packet parser with a fixed hardware design that supports different functionality by changing a program stored in an embedded memory that is derived from the parser section of a P4 code. This method replaces pipeline of parsing blocks with a single parsing block and offers an 11Gb/s data-rate on Xilinx Virtex-7 FPGA, consuming 312 LUTs and 1135 FFs.