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Presentations
Selective Clock Gating Based on Comprehensive Power Saving Analysis
Presented Date:Jul 05, 05:50pm UTCID: 2304
Presenter(s): Sora Park
A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers
Presented Date:Jul 05, 05:50pm UTCID: 2318
Presenter(s): Shi Bu
SQNR-Based Layer-Wise Mixed-Precision Schemes with Computational Complexity Consideration
Presented Date:Jul 05, 05:50pm UTCID: 2325
Presenter(s): Hana Kim
Chairs
Chair(s)
Display Name
Sri Navaneeth Easwaran
- Affiliation
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AffiliationTexas Instruments Inc
- Country