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Presentations
SNNIM: A 10T-SRAM Based Spiking-Neural-Network-in-Memory Architecture with Capacitance Computation
Presented Date:Jul 04, 05:53pm UTCID: 1889
Presenter(s): Bo Wang
Author(s): Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si
A Lightweight Spiking GAN Model for Memristor-Centric Silicon Circuit with On-Chip Reinforcement Adversarial Learning
Presented Date:Jul 04, 05:53pm UTCID: 2134
Presenter(s): Jing Lu
A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-Approximation and Single-Slope Stages for Computing in Memory
Presented Date:Jul 04, 05:53pm UTCID: 2156
Presenter(s): Wuyu Fan
Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting
Presented Date:Jul 04, 05:53pm UTCID: 2159
Presenter(s): Chenjia Xie
Chairs
Chair(s)
![Vishal Saxena Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/2539001.jpg?h=589afc61&itok=m6Hr6VkT)
Display Name
Vishal Saxena
- Affiliation
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AffiliationUniversity of Delaware
- Country