D2L-E
ISCAS 2020
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Technical Lecture and Demo

Hardware Security for Logic, Circuits & Architectures II

Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors

Presented Date:Jul 04, 07:23pm UTC
Presenter(s): Seetal Potluri
Author(s): Qinhan Tan, Seetal Potluri, Aydin Aysu

Modeling SAT-Attack Search Complexity

Presented Date:Jul 04, 07:23pm UTC
Presenter(s): Saran Phatharodom
Author(s): Saran Phatharodom, Nagarajan Kandasamy, Ioannis Savidis

Reducing Logic Locking Key Leakage Through the Scan Chain

Presented Date:Jul 04, 07:23pm UTC
Presenter(s): Kyle Juretus
Author(s): Kyle Juretus, Ioannis Savidis

RNN-Based Detection of Fault Attacks on RSA

Presented Date:Jul 04, 07:23pm UTC
Presenter(s): Troya Cagil Köylü
Author(s): Troya Cagil Köylü, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil

A New Logic-Locking Scheme Resilient to Gate Removal Attack

Presented Date:Jul 04, 07:23pm UTC
Presenter(s): Jingbo Zhou
Author(s): Jingbo Zhou, Xinmiao Zhang
Chair(s)
Xinmiao Zhang Headshot
Xinmiao Zhang
Affiliation
Ohio State University
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Seetal Potluri Headshot
Seetal Potluri
Affiliation
North Carolina State University
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