In this paper, a novel PCDSA based on the three-input C-element is proposed to tolerate the SEDU. By using a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit, hybrid simulations have been performed to demonstrate its functionality. Simulation results show that it can fully tolerate the SEDU when the amount of the deposited charge Qinj reaches up to 2 pC. In the worst case where the Qinj is 2 pC, it can achieve a small recover time of 1.3368 ns and low recover energy dissipation of 1.967 pJ with the optimized VDD of 1 V.