We proposed a voltage-division (VD) based computing approach and its circuit implementation in two-transistor-tow-resistor (2T2R) RRAM cell arrays, which can realize energy-efficient, sign-aware, and robust deep neural network (DNN) processing. A readout technique, namely the input-dependent sensing control (IDSC) scheme, is also introduced for power saving. On this basis, a 400kb VD-based RRAM nvCIM is silicon verified. It achieves 2.54 times power reduction compared to that of the ones rely on conventional weighted-current summation (WCS) mechanism, a peak energy-efficiency of 42.6 TOPS/W and a minimum latency of 15.98 ns.