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Presentations
An Efficient Hardware Architecture for DNN Training by Exploiting Triple Sparsity
Presented Date:Jul 04, 06:22pm UTCID: 1349
Presenter(s): Jian Huang
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models
Presented Date:Jul 04, 06:22pm UTCID: 1417
Presenter(s): Xiaoling Yi
Author(s): Xiaoling Yi, Jiangnan Yu, Zheng Wu, Xiankui Xiong, Dong Xu, Chixiao Chen, Jun Tao, Fan Yang
A High-Speed Codec Architecture for Lagrange Coded Computing
Presented Date:Jul 04, 06:22pm UTCID: 1441
Presenter(s): Bohang Xiong
A 11.6µW Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization
Presented Date:Jul 04, 06:22pm UTCID: 1506
Presenter(s): Xinru Jia
Author(s): Xinru Jia, Haozhe Zhu, Yunzhengmao Wang, Jinshan Zhang, Xinru Jia, Xinru Jia, Xinru Jia, Chixiao Chen, Chixiao Chen
BSRA: Block-Based Super Resolution Accelerator with Hardware Efficient Pixel Attention
Presented Date:Jul 04, 06:22pm UTCID: 1619
Presenter(s): Dun-Hao Yang
Chairs
Chair(s)
Display Name
Hongbin Sun
- Affiliation
-
AffiliationXi'an Jiaotong University
- Country
Display Name
Robert Chen-Hao Chang
- Affiliation
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AffiliationNational Chung Hsing University
- Country