A new data retention flip-flop, DRFF-Lite, which is designed based on the conventional master-slave flip-flop is proposed in this paper. No additional data retention circuitry is required by DRFF-Lite to implement the low-leakage data retention sleep mode, thereby providing easy and energy-efficient mode transitions. Due to the simplified topology, DRFF-Lite achieves up to 40% layout area savings as compared to the state-of-the-art data retention flip-flops in a 40-nm CMOS technology. Furthermore, DRFF-Lite reduces the sleep mode leakage power consumption, active mode leakage power consumption, active power consumption, and mode transition energy consumption by up to 31.5%, 60%, 18.5%, and 85.9%, respectively, under the impact of process parameter variations, while providing similar critical path propagation delay as compared to the state-of-the-art data retention flip-flops.