This paper presents an exhaustive comparison of two different techniques for In-Memory Computing in SRAM: BSA, which employs bit-serial arithmetic, and BPA, which uses bit-parallel arithmetic. The results are analyzed for both approaches with ten different sub-array configurations ranging from 128x128 to 2048x2048. The key observation is that the BPA yields at least 15% better (lower) EDP than BSA at large (2048x2048) sub-array sizes. The BSA yields 4x lower delay on an average, while the BPA yields nearly 6× lower dynamic energy. Hence, the choice of the IMC architecture needs to be made depending on the application (low energy vs. high performance).