This paper presents a new approximate adder with reduced error and optimized design metrics. The proposed approximate adder is based on a modification of an existing approximate adder HERLOA and is called modified HERLOA or M-HERLOA in short. We considered a systematic modification of HERLOA to derive an optimum M-HERLOA. We evaluate the performance of M-HERLOA and other approximate adders in terms of the error characteristics and design metrics. We calculated popular error parameters such as mean absolute error and root mean square error for the approximate adders. We estimated the design metrics of approximate adders based on FPGA and ASIC-type (standard cell based) implementations. We also compare the performance of the accurate adder and different approximate adders based on a digital image processing application by evaluating the peak signal-to-noise ratio and structural similarity index metric. The proposed M-HERLOA reconstructs a digital image that is visually similar to the image reconstructed using the accurate adder. This is achieved with M-HERLOA simultaneously enabling following reductions in design metrics compared to the accurate adder for a 32-bit addition: (i) 9.5% reduction in delay, 9.1% reduction in total power, 7 LUTs less and 18 flip-flops less for a FPGA based implementation, and (ii) 18% reduction in delay, 26.7% reduction in total power and 23.1% reduction in area for an ASIC-type implementation.