An 81-99 GHz tripler for wireless transceiver LO generation is presented in this paper. The inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is used to further suppress the fundamental signal. The tripler achieves more than 40 dBc of all the unwanted harmonics. The tripler reaches a -2.6-dBm output power at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.