This paper presents the complete transistor-level design of a Low-Noise-Amplifier (LNA) in CMOS 28 nm bulk technology for sensing the weak extracellular neuro-potentials signals in Electrolyte-Oxide-MOS (EOMOS) Brain-Chip Interfaces. The proposed LNA adopts an efficient pseudo-resistor topology that allow to synthesize a stable resistance (in the tens of GΩ order) without any external calibration. The LNA has 2.4 Hz minimum passband frequency performing 7.8 µVRMS and 8.8 µVRMS input-referred noise power at 1 Hz - 300 Hz (Local Field Potential) and 300 Hz – 5 kHz (Action Potentials) bandwidth, respectively. The device consumes 2.4 µW power and has been designed in 28 nm CMOS technology.