This presents a fully-synthesizable cyclic Vernier time-to-digital converter (TDC) which cancels the offsets by a quad-edge offset cancellation (QOC) scheme. The system delays its internal clocks and uses the clock offsets to compensate for many types of offsets altogether, which includes the wiring mismatches, the duty cycle skews, and the long-term jitters of the clocks. During calibration, the QOC-TDC measures the offsets of the clock paths. The measured offsets are then canceled in the normal mode. An additional scheme of coarse-fine boundary synchronization further enhances the output monotonicity. Consisting of only standard library cells offering fully-automated implementation, the QOC-TDC achieves a 19-bit range, a 4.5-ps resolution, and the throughput of 22MS/s, while drawing 3.4mW from a 1.0V supply, as shown by the post-layout simulations in 28nm CMOS.