This work demonstrates a co-design of an injection-locked ring oscillator locked to a FBAR-based PLL, both designed in CMOS. The proposed co-design gives us the best of both worlds: low phase noise and jitter from FBAR PLL, and deskew and multi-phase generation abilities from ILRO. The resulting co-design achieves overall 1.2ps RMS jitter, and -116dBc/Hz @1MHz offset. It is much better than a typical CMOS ring oscillator based PLL, and also slightly better than a LC based PLL. An analysis of phase noise contribution is also made and compared with the measurement results. In addition to achieving low timing jitter performance, the proposed design can generate 8 phases and ±45° deskew range at no additional cost, which are beneficial to use in high-speed serial links and ADCs. The designs consume a total power of 1.63mW with less than 0.1 mm2 die area in CMOS.