A reference-less frequency-detector (FD)-less single-loop quarter-rate bang-bang clock and data recovery circuit (BBCDR) achieves a wide frequency acquisition. By the virtue of the proposed deliberate-current-mismatch charge-pump pair and wide-tuning-range 8-phase ring oscillator, the low-power single-sided capture scheme is developed by eliminating the high-speed power-hungry circuits. Fabricated in 65-nm CMOS, our non-return-zero prototype covers 10.8 to 37.4 Gb/s data-rate variation, while scoring a 110.4% capture range with up to 4.63-[(Gb/s)/μs] acquisition speed and 1.3-pJ/bit energy efficiency.