In-SRAM computing generally presents a very distinct bitline discharging behavior, so that a suitable sensing topology is vital for the good performance of a compute SRAM. Two recent sensing topologies, namely the symmetric single-ended sensing amplifier (SA) and the asymmetric differential SA, have been proposed in previous designs. However, it is not so straightforward to see which of the two sensing topologies is better in terms of read delay and read energy consumption, and no previous work has ever had a clear answer to this. In this paper, we perform a comprehensive analysis of these two sensing topologies, and find that the asymmetric differential SA performs faster than the symmetric single-ended SA. In addition, we propose an improved asymmetric differential SA with a novel pre-charging scheme. Compared to the state-of-the-art, experimental results show that our proposed SA has reduced its read delay by 17% and the total read energy by 8%, in an 8Kb compute SRAM using a 55nm CMOS technology.