Embedded memories occupy an increasingly dominant portion of the area and power budgets of modern SoCs and are also a limiting factor in VDD scaling. GC-eDRAM is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires an additional boosted voltage supply for successful write operations. This work presents a novel technique that uses the same negative voltage applied to the write port in many GC-eDRAMs topologies to expedite the read operation and/or further increase the DRT by using it during read operations. An 8 kbit memory macro was implemented in a 28nm FD-SOI technology, demonstrating over 20X read latency reduction, an order-of-magnitude longer DRT, and up-to 4 order-of-magnitude lower retention power consumption over a conventional 2T GC-eDRAM.