Presentations
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance
Presented Date:Jul 08, 11:11am UTCPresenter(s): Jue Wang
A Segmented SAR/SS ADC with Digital Error Correction and Programmable Resolution for Column-Parallel Sensor Arrays
Presented Date:Jul 08, 11:11am UTCPresenter(s): Jacob Rosenstein
A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS
Presented Date:Jul 08, 11:11am UTCPresenter(s): Ayca Akkaya
A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET
Presented Date:Jul 08, 11:11am UTCPresenter(s): Yan Zheng
A Low-Power and Area-Efficient Analog Duty Cycle Corrector for ADC's External Clocks
Presented Date:Jul 08, 11:11am UTCPresenter(s): Nanqi Liu
A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS
Presented Date:Jul 08, 11:11am UTCPresenter(s): Qian Chen
Active Noise Shaping SAR ADC Based on ISDM with the 5MHz Bandwidth
Presented Date:Jul 08, 11:11am UTCPresenter(s): Bo Gao
Multi-Bit Incremental Converters with Optimal Power Consumption and Mismatch Error
Presented Date:Jul 08, 11:11am UTCPresenter(s): Waqar Ahmed Qureshi
Chairs
Chair(s)
Display Name
Jorge Fernandes
- Affiliation
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AffiliationINESC-ID
- Country
Display Name
Kangmin Hu
- Affiliation
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AffiliationInnogrit Corp.
- Country