The use of CMOS circuits for the control and readout of qubits is a step that will speed up the process of creating more complex qubit arrays than is currently possible. This paper focuses on the characterization strategies and challenges entailed in using CMOS technology at low cryogenic temperatures, where qubits can operate, replacing long interconnecting cables to benchtop instruments. The restricting cooling power of a cryostat, determines the system design between the quantum layer of qubits and the classical layer of circuits. Several architectures and device technologies have been proposed to house both qubits and circuits at the same stage of a cryogenic chamber. New cryogenic transistor, devices and silicon layer models are needed for a certain CMOS technology and process to be used for CryoCMOS circuit design at a selected temperature. Characterization approaches and the necessary extracted parameters for modelling are being determined and can potentially form a new protocol as the system becomes more complex than a typical probe station.