This paper presents a 20-Gb/s optical receiver consisting of a novel transimpedance amplifier (TIA), three active feedback Cherry-Hooper limiting amplifiers (LA) and DC offset cancellation loop. A novel cross-coupled dual-feedback loop TIA is proposed to reduce the input impedance and enhance the tolerance of large input capacitance without deterioration of the transimpedance gain. Moreover, not any extra noise, power consumption or chip area is introduced. Implemented in 65-nm CMOS technology, the receiver achieves 73.1 dBΩ transimpedance gain with a bandwidth of 10.2 GHz and a data rate of 20 Gb/s, while the input referred noise (IRN) current is below 30.5 pA/√Hz from 1 to 10.2 GHz. The core circuit consumes a DC power of 9.6 mW from a 1.2V supply (without output buffer) and occupies a layout area of 0.042 mm2.