Profile

Aditya Japa received B.Tech. degree in Electronics and Communication Engineering from Sree Chaitanya College of Engineering, Karimnagar (J.N.T.U Hyderabad), Telangana, India, in 2012 and the M.Tech. degree in VLSI Design from Vignan’s University, Andhra Pradesh, India, in 2015. He was a JRF under a DST project titled “Design, Analysis and Benchmarking of Energy efficient Hetero-junction tunnel FET based Digital, Analog and RF Building blocks during 2015-16. He is currently pursuing Ph.D. in Electronics and Communication Engineering from DSPM International Institute of Information Technology, Naya Raipur, India. His current research interest includes Low Power Circuit design, emerging transistor technologies (Tunnel FETs) and Hardware security based circuit design.