In this presentation, we argue and provide Non-Equilibrium Green’s Function Landauer formalism-based simulation evidence that in spite of Graphene’s bandgap absence, Graphene Nanoribbons (GNRs) can provide support for energy-effective computing. We start by demonstrating that: (i) band gap can be opened by means of GNR topology and (ii) GNR’s conductance can be molded according to some desired functionality, i.e., 2- and 3-input AND, NAND, OR, NOR, XOR, and XNOR, via shape and electrostatic interaction. Afterward, we introduce a generic GNR-based Boolean gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the gate inverted Boolean function, and, by properly adjusting GNRs' dimensions and topology, we design and evaluate by means of SPICE simulations inverter, buffer, and 2-input GNR based AND, NAND, and XOR gates. Compared with state-of-the-art graphene FET and CMOS-based counterparts the GNR-based gates outperform its challengers, e.g., up to 6x smaller propagation delay, 2 orders of magnitude smaller power consumption while requiring 1 to 2 orders of magnitude smaller active area footprint than 7nm CMOS equivalents. Finally, to get a better inside into the practical implications of the proposed approach, we present Full Adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of Error Correcting Codes codecs, that outperforms a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6x smaller delay, 3 orders of magnitude less power consumption while requiring 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based n-bit Ripple Carry Adder, whose performance is linear in the Carry-Out path delay, will be 108x faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to DC-noise characteristics, while performance-wise has a 3x smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue toward future competitive carbon-based nanoelectronics.