The explosive growth of the number of transistors produced annually in the IOT world requires design methods capable of significantly reducing power consumption. Power optimization must be done at all levels of design abstraction, system, computer architecture till the physical design. This tutorial focuses on the optimization at physical design level. Nowadays, most circuits and systems are using more transistors than is needed. We will show some strategies to reduce the number of transistors and by consequence decrease power consumption, mainly static power. The reduction of the number of transistors also helps to improve routability and reliability. The reduction of the transistor count demands new tools to automatically generate the layout of any transistor network. EDA tools that can perform this task will be described.