SAR is widely used for medium resolution applications due to its simplicity, scaling compatibility, and low-power consumption. However, its power efficiency degrades as the resolution increases due to its tight requirement on the comparator noise and the exponentially growing capacitor DAC array. By contrast, DS ADC is a popular architecture for high-resolution applications. Taking advantage of noise shaping, it can achieve high resolution with a low-resolution quantizer and DAC. However, it typically requires the use of op-amps that are power hungry and scaling unfriendly. This talk will present latest noise-shaping (NS) SAR ADCs that aim to combine the merits of SAR and DS ADCs while simultaneously obviating their drawbacks. It includes both cascade of integrators with feed-forward (CIFF) and error-feedback (EF) NS-SAR architectures. It covers various types of hardware implementations, including both active and passive loop filters and adders. It also discusses interesting extensions of NS-SAR ADCs, including time-interleaved NS-SAR and continuous-time (CT) DS ADC with NS-SAR quantizer.