This paper presents a single-slope analog-to-digital converter (SS-ADC) with a proposed zero-crossing (ZC)-prediction-based power-gating technique for low-power complementary metal-oxide-semiconductor (CMOS) image sensor applications. The proposed ZC prediction utilizes the DC gain difference between the preamplifier and main comparator in the SS-ADC without an additional ramp signal. For a consistent prediction with a low-power operation, the constant charge bias amplifier (CQBA) is implemented as a preamplifier, which exhibits input level independent output common-mode and gain response. The proposed 10-bit SS-ADC is demonstrated with a 110-nm CMOS image sensor process for a 640 × 480 image resolution and 120 frames/s. The simulation results show that the CQBA output common-mode and gain response only vary by 1% and 6.4%, respectively. Furthermore, the overall power consumption of the sensor is reduced by about 80%, achieving the high energy efficiency (50.3 fJ/conv.-step of the figure of merit).