A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end that employs a clock strategy is proposed to support software-defined radios (SDRs). It includes a capacitively cross-coupled common-gate LNTA to amplify and convert the RF voltage to a current, a passive mixer to down-convert the RF current at 4×the LO frequency to the IF current using a clock strategy, an active-inductor (AI) technique to improve the noise-figure (NF) performance, and a TIA to convertthe IF current to a voltage at the output. To achieve low power consumption the receiver features: current-reuse between the LNTA and the BB circuits; current-mode harmonic recombination at the output of the passive mixer; and a clock strategy to reduce the dynamic power consumption of the clock generation for the dividers and the LO buffers. The proposed receiver is implemented in 22-nm CMOS technology and occupies an active area of 0.13 mm2. In the nominal condition, at an IF of10 MHz and an RF of 2.4 GHz, it achieves a voltage gain of 36 dB, a double-sideband (DSB) NF of 5.2 dB, S11 of less than −10 dB and an IIP3 of −18.5 dBm while consuming 2.44 mA from a 1.2 V supply voltage.