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Video s3
    Details
    Presenter(s)
    Chihiro Matsui Headshot
    Display Name
    Chihiro Matsui
    Affiliation
    Affiliation
    University of Tokyo
    Country
    Author(s)
    Display Name
    Chihiro Matsui
    Affiliation
    Affiliation
    University of Tokyo
    Display Name
    Eitaro Kobayashi
    Affiliation
    Affiliation
    University of Tokyo
    Affiliation
    Affiliation
    University of Tokyo
    Display Name
    Shinichi Takagi
    Affiliation
    Affiliation
    University of Tokyo
    Display Name
    Ken Takeuchi
    Affiliation
    Affiliation
    University of Tokyo
    Abstract

    This paper proposes fast and small-area FeFET-based voltage-sensing analog Computation-in-Memory (CiM) for hyperdimensional computing (HDC) by eliminating large-scale digital circuit overhead. In both training and inference of HDC, MAP (bit-wise XOR, bit-wise majority rule, and 1-bit shift) of hypervectors (HVs) is operated by Partially added Text HV FeFET CiM and Text HV FeFET. In inference, Similarity search FeFET CiM obtains classification result. By taking an example of Language classification problem, the proposed voltage-sensing FeFET CiM for HDC encodes HV in training by 5,000 times faster and smaller area than the conventional method.

    Slides
    • Versatile FeFET Voltage-Sensing Analog CiM for Fast & Small-Area Hyperdimensional Computing (application/pdf)