The successive cancellation flip (SCF) algorithm has been proposed to improve the error correction performance of polar codes. For hardware implementation of the SCF decoder, additional memories for storing intermediate decoding results are required not to return to the first bit during additional attempts in decoding. This paper proposes a uniformly segmented SCF decoder with memory reduction methods. We analyze the critical set distribution and uniformly segment the entire codeword to reduce the memory for storing the intermediate decoding results. The proposed decoder is implemented in Verilog HDL and synthesized using the Samsung 65 nm standard cell library. It shows 7% smaller area compared with the SC list (SCL) decoder with the list size L=2. Compared to the recent SCF decoder and fast-SSCF decoder, the proposed decoder has 34% better throughput and 23% less area respectively.